Implementation of Programmable n-bit Pseudo Random Sequence Generator using 45 nm Technology

Abstract

In recent times with the advent of computers, programmers recognized the necessity for a means of introducing randomness into a computer program. Pseudo-random numbers generates necessary values for processes that require randomness, such as creating test signals or for synchronizing transmitting and receiving devices in a spread spectrum transmission. It is not possible to generate truly random numbers from deterministic thing like computers so PRSG is a technique developed to generate random numbers using a computer. Our proposed system is used to implement multiple polynomials of degree 2 to 16 in Incisive and Genus Cadence Tool. This system can be implemented in statistical analysis, and modern-day computer simulations, digital cryptography and generation of OTP.

Introduction

I. INTRODUCTION

Pseudorandom Sequence Generator (PRSG) refers to an algorithm that uses mathematical formulas to produce sequences of random numbers. PRSGs generate a sequence of numbers which will approximate the properties of random numbers. Many sequences are generated in a short time and can also be reproduced later, if the beginning point in the sequence is known. Therefore, the numbers are deterministic and efficient. Linear Feedback Shift Registers are shift registers (LFSR) with input bits that are a linear function of their previous state.  An LFSR generates pseudo-random bit sequences that can be used in logical circuit testing. The LFSR is driven by XORing/XNORing multiple bits which is popularly termed as Feedback. The primitive polynomial selected determines the feedback path. In our method, XNOR gate is used in the feedback path for the MUX 8x1. The degree of the primitive polynomial is used to tell number of flip-flops used in this method. If the number of bits is given by n, the longest possible sequence length produced can be given by 2n−1. Primitive polynomial refers to the polynomial that generates the longest possible sequence. Non-Primitive polynomials produce sequence of length should always be lesser than 2n–1.

II. LITERATURE SURVEY

In the paper, [1] “Programmable Variable Length Pseudo Random Sequence Generator” published in the year 2022 have its features like producing variable length sequence with high speed operation of the circuit using XNOR gates.

Another reference paper cited, [2] “Design of Pseudo Random using Non-Linear Feedback Shift Register” published in the year 2022 has its features like low speed operation. The design in this paper does not support error checking and error correction.

Another reference paper titled, [4] “Low power Programmable Pseudo Random Word Generator” published in the year 2008 has a unique feature as, toggles can be set in advanced i.e., ‘pre-selected toggles’ and used as conventional pseudo random sequence generator.

Another reference paper titled, [3] “A 15-Gb/s 0.0037-mm2 0.019-Pj/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator” published in the year 2020, which is suitable for compact designs with high power and less efficient.

III. PROPOSED DESIGN

In this project, we consider polynomial of degree 2 to 16 which further includes one 8x1 Multiplexer, number of flip flops are 16 and 8 XNOR gates are connected as input for the MUX.  As shown in the figure .The output of the MUX is given to the first D flip flop d_0 and for remaining flip flops  linear shifting takes place. The randomness can be obtained from different polynomial and a particular pattern is selected using pattern selector.

IV. METHODOLOGY

The implementation of this project is done in Cadence tool, further synthesis is done in Genus and physical design is implemented with help of Innovus tool. The output sequence depends on number of bits ‘n’. A 8x1 is used to vary the output sequences of linear function. Different feedback paths which are based on 8 different polynomials of degree ‘n’ are given as input to 8x1 MUX. The pseudo code for proposed method for the above figure n=5 is as shown in the Fig. 1.

Conclusion

The proposed method is able to generate Variable-length Pseudo Random Sequences according to the user’s input. As the previous methods of generating a pseudo random sequences are less efficient and dissipate high power as shown in the TABLE IV. This project is implemented with low power and highly efficient pseudo random sequences. The pseudo-random sequence generators are marked by evolution in security, hardware implementations, application-specific, Equalized, interdisciplinary collaboration, and ethical considerations. By Communicating with these challenges and opportunities, PRSG considered to progress as tools for establishing randomness, security, and reliability in diverse computing applications. PRSGs play a crucial role in decision-making processes in diverse sectors, addressing concerns related to bias, fairness, and explicit. Future developments should prioritize ethical principles to be responsible and standardized use of randomness in computational systems. Some of the well known applications are Hardware-based PRSGs, grasping determined hardware components like field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), provide better performance and efficiency compared to software-based approaches. Future developments primarily focus on optimizing hardware architectures for specific implementations and objectives.

References

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Copyright

Copyright © 2024 Mrs. S. Aruna, Ch. Soumya Pranathi, A. Siva Madhuri, K. Neha . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.